1. Field of the invention
The present invention relates to an input signal reading circuit, and more specifically to an input signal reading circuit for stably reading a noisy input signal with a small amount of delay and a high degree of fidelity.
2. Description of related art
Japanese Patent Application Pre-examination Publication No. JP-A-57-087232 (the content of the which is incorporated by reference in its entirety into this application, and also an English abstract of JP-A-57-087232 is available from the Japanese Patent Office and the content of the English abstract of JP-A-57-087232 is also incorporated by reference in its entirety into this application) discloses one typical prior art input signal reading circuit, which will be now described with reference to FIGS. 1 and 2. FIG. 1 is a simplified block diagram of the prior art input signal reading circuit disclosed in JP-A-57-087232, and FIG. 2 is a timing chart illustrating an operation of the prior art input signal reading circuit disclosed in JP-A-57-087232.
As shown in FIG. 1, the prior art input signal reading circuit disclosed in JP-A-57-087232 includes an integral counter, namely, an up counter 5 for sample-counting an input signal S.sub.1, and a timing pulse generator 6 for generating a sampling clock and a read timing pulse S.sub.8. The up counter 5 is controlled by the input signal S.sub.1 to count the sampling clock only when the input signal S.sub.1 is at a high level, and to output a signal S.sub.7 of a high level when a count value of the up counter 5 is equal to or larger than a predetermined constant value (threshold value) preset in the up counter itself. When the count value of the up counter 5 is smaller than the predetermined constant value, namely, when the count value of the up counter 5 has not yet reached the predetermined constant value, the up counter 5 outputs the signal S.sub.7 of a low level. When the read timing pulse S.sub.8 is generated by the timing pulse generator 6, the up counter 5 is reset or cleared, to re-start a count-up from an initial value. On the other hand, a D-type flipflop 7 latches the signal S.sub.7 at each time the read timing pulse S.sub.8 is generated, and a Q output of the D-type flipflop 7 is outputted as a read-out output signal S.sub.9 of the input signal S.sub.1.
Thus, by appropriately selecting the frequency of the sampling clock and a period of the read timing pulse S.sub.8, a noise contained in the input signal S.sub.1 is removed as shown in the timing chart of FIG. 2.
As seen from the timing chart of FIG. 2, the prior art input signal reading circuit is constructed to detect, in synchronism with the read timing pulse S.sub.8, whether or not the count value of the up counter 5 reaches the predetermined constant value, namely, whether or not the up counter 7 outputs the output signal S.sub.7 of the high level. Furthermore, the up counter 5 is reset in synchronism with the read timing pulse S.sub.8, namely, at the period of the read timing pulse S.sub.8. Therefore, although the count value of the up counter 5 has already reached the predetermined constant value, the high level output signal of the up counter 5 is not detected unless the read timing pulse S.sub.8 is outputted In addition, since advancement of the counting is delayed by the low level noise, if the count value of the up counter 5 does not reach the predetermined constant value until the read timing pulse S.sub.8 is outputted, the count value of the up counter 5 is reset, so that the high level output signal of the up counter 5 is not detected. As a result, the detection timing is significantly delayed, as shown in a left half of FIG. 2, and in extreme case, although a high level input signal is received, it is not possible to detect the input signal, as shown in a right half of FIG. 2.